1. Field of the Invention
The present invention relates to an overlay vernier pattern and a method for measuring multi-layer overlay alignment accuracy on a substrate, and more particularly, to an overlay vernier pattern and a method that measures overlay alignment of a photoresist layer with a plurality of material layers.
2. Description of the Prior Art
Semiconductor integrated circuits undergo a variety of processing steps during manufacture, such as masking, resist coating, etching, and deposition. In many of these steps, material is overlaid or removed from the existing layer at specific locations in order to form the desired elements of the integrated circuit. Proper alignment of the various process layers is therefore critical.
Registration is typically used to measure layer-to-layer alignment accuracy for a semiconductor process. Registration involves comparing a position of a subsequent layer to a position of an existing layer by overlaying a distinct pattern on a matching pattern that is previously formed on the existing layer. At least an alignment mark is formed in the distinct pattern and the matching pattern. A distance between the alignment mark in the subsequent layer and the alignment mark in the existing layer provides a measure of misalignment between these two layers. Currently available registration structures include Box-in-Box visual verniers and Bar-in-Bar visual verniers to determine the extent of registration, i.e., the amount of alignment offset.
Please refer to FIG. 1, which shows a top view of a prior-art overlay vernier pattern for measuring layer-to-layer overlay alignment accuracy. FIG. 2 shows a prior-art schematic cross-sectional view along line 1A–1A″ of the top view in FIG. 1. In FIG. 1, a typical Bar-in-Bar overlay vernier pattern 20 is shown, for example by forming a plurality of alignment marks 22 in a material layer 10 and a plurality of alignment marks 24 in another material layer 12 over the material layer 10, as depicted in the cross section in FIG. 2. The alignment marks 22 and 24 are formed in a scribe line of a test wafer and are symmetric to a center of the overlay vernier pattern 20. The material layer 10 can be a silicon substrate, a conductive layer or an insulating layer. The material layer 12 can be a conductive layer or an insulating layer. The alignment marks 22 and 24 are formed by positive photoresist or negative photoresist, having a pattern such as a recess buried in the material layers 22 and 24 or as a column protruded from an underlying material layer. Ideally, the alignment marks 22 are after-etch-inspection (AEI) trench structures formed by methods known by those versed in the art. The alignment marks 24 are after-development-inspection (ADI) photoresist column patterns.
When measuring misalignment of the material layer 12 to the material layer 10, a distance B1 between a midpoint of an alignment mark 24 and a midpoint of an alignment mark 22 adjacent to the alignment mark 24 is measured using an alignment accuracy measurement tool, such as a scanning electron microscope. In addition, a distance B2 between a midpoint of another alignment mark 24 and a midpoint of an alignment mark 22 adjacent to this alignment mark 24 is also measured using the same alignment accuracy measurement tool. Following this, a difference between the distances B1 and B2 is calculated, so as to get an alignment offset between the material layers 10 and 12. Similarly, when measuring misalignment between the material layer 12 and a material layer (not shown) over the material layer 12, another overlay vernier pattern, which includes a plurality of alignment marks in the material layer 12 and in the material layer over the material layer 12, is formed in another region of the scribe line.
However, with the shrinking dimensions of modern integrated circuits, multi-layer structure is developed for a chip. For a three-layer structure or a more complicated structure, layer-to-layer alignment accuracy measurement is performed, respectively, for any two of the layers to occupy a scribe line area and waste measuring time. Therefore, development of an overlay vernier pattern and a measurement method to effectively measure the overlay alignment accuracy of the multi-layer structure has become important.